πŸ“Š Memory Hierarchy

PHASE 1 β€’ MODULE 1.5
PROCESSOR
CPU Core
L1 Cache
64 KB
~4 cycles
L2 Cache
512 KB
~12 cycles
L3 Cache
32 MB
~40 cycles
RAM (DDR5)
32 GB
~200 cycles
SSD (NVMe)
1 TB
~50,000 cycles
D
0
0
Total Cycles
0
Cache Hits
0
Cache Misses
--%
Hit Rate

Memory Request

1x

Scenarios

L1 Cache Contents

---- Empty
---- Empty
---- Empty
---- Empty

Latency Comparison

L1
4 cycles
L2
12 cycles
L3
40 cycles
RAM
200 cycles
SSD
50K+ cycles
If L1 = 1 second, RAM = 50 seconds, SSD = 3.5 hours
πŸ’₯ HOLY SHIT MOMENT
"Your CPU is 1,000Γ— faster than your RAM. Physics won't let us have memory that's both fast AND large β€” so we layer caches between them."